1. Field of the Invention
The present invention relates to signal processing circuits forming feedback control loops including filters and, more particularly, to a signal processing circuit and a signal processing method that compensate loop delays. The present invention also relates to a playback apparatus in which the signal processing circuit is applied to a phase locked loop (PLL) circuit that controls the phase and frequency of a signal read out from a recording medium.
2. Description of the Related Art
Some systems of playing back data recorded on optical disk recording media, such as compact discs (CDs), digital versatile disks (DVDs), or Blu-Ray discs (BDs) (registered trademark) discs, or magnetic recording media, such as hard disk drives (HDDs), and some data communication systems perform digital sampling of readout signals and reception signals. In the sampling of such readout signals and receptions signals, PLL circuits are used so that the sampling values at appropriate sampling times are measured. In other words, the PLL circuits are used to appropriately control the sampling times of input signals or to perform waveform interpolation to the input signals (an interpolated timing recovery (ITR) method described below) in order to measure the sampling values at the appropriate sampling times.
An increase in the processing speeds of the PLL circuits used in the digital sampling is demanded in order to respond to an increase in the recording densities of recording media and an increase in the data communication speed in recent years. In such a situation, pipeline processing is generally applied to the PLL circuits.
However, with the pipeline processing, the presence of a pipeline delay causes the corresponding loop delay to occur in a feedback control loop. In other words, the loop delay degrades the pull-in performance of the PLL. The loop delay can cause the feedback control loop to lose the phase margin and, specifically, can cause a decrease in the pull-in speed (a delay in the convergence time). In addition, a capture range is decreased as the loop delay is increased. The capture range means a range over which the PLL can pull in any frequency difference.
Various technologies in related art are proposed in, for example, Japanese Unexamined Patent Application Publication No. 8-107352, Japanese Unexamined Patent Application Publication No. 2007-122774, and U.S. Pat. No. 6,236,343 in the above situations.
Of the above documents, Japanese Unexamined Patent Application Publication No. 8-107352 concerns a technology for increasing the speed of phase locking.
Japanese Unexamined Patent Application Publication No. 2007-122774 according to the assignee of the present application proposes a technology for pulling in a frequency difference and, then, pulling in a phase difference to expand the capture range.
The technologies disclosed in Japanese Unexamined Patent Application Publication No. 8-107352 and Japanese Unexamined Patent Application Publication No. 2007-122774 can be used to take certain measures against the decrease in the pull-in speed involved in the loop delay or the decrease in the capture range. However, it is not possible to fundamentally resolve the problems concerning the loop delay.
Specifically, with the technology disclosed in Japanese Unexamined Patent Application Publication No. 8-107352, if the frequency difference is present in a playback waveform, it is not possible to fully pull in the phase even at a higher pull-in speed because of the presence of the frequency difference and, if a longer loop delay occurs, the device can possibly be damaged. In other words, the phase locking can be performed at a high speed whereas the capture range is sacrificed.
With the technology disclosed in Japanese Unexamined Patent Application Publication No. 2007-122774, since the phase difference is converged after the frequency difference is converged, the final convergence time is given by adding the convergence time of the phase difference and that of the frequency difference. Accordingly, there is a problem in that the convergence time becomes longer than the time when both the frequency difference and the phase difference are concurrently pulled in. In other words, the capture range can be expanded whereas the convergence time is sacrificed.
In order to overcome the delay in the convergence time and the decrease in the capture range which are caused by the loop delay, it is effective to compensate the loop delay itself. Accordingly, technologies for using a Kalman filter to compensate the loop delay of the PLL are proposed in U.S. Pat. No. 6,236,343, “Application of Kalman Filters With a Loop Delay in Synchronization” Ara Patapoutian, IEEE Transactions on Communications, Vol. 50, No. 5, May 2002 (hereinafter referred to as Reference Document 1), and “Timing Recovery Loop Delay Compensation by Optimal Loop Gains” Jin Xie and B. V. K. Vijaya Kumar, Data Storage Center (DSSC), Electrical and Computer Engineering Department, Carnegie Mellon University, IEEE ICC 2006 Proceedings (hereinafter referred to as Reference Document 2).